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Altera_Forum's avatar
Altera_Forum
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14 years ago

A simple problem with bidirectional bus in VHDL

The situation is: I have one bidirectional bus and two registers and two buffers tri-state. Just as you can see at this link: @@@@dl.dropbox.com/u/288645/Drawing1.png@@@@ But when I open the si...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

I think you're lacking a "data <= (others => 'Z');" in the registrador module.

Thus, "registrador" is driving "U", not "Z" into that signal.

That said... avoid using tri-state for anything but the top level modules.

FPGA's don't have tri-state buffers in the internal logic (only in the I/O cells) and thus the tool will simply emulate tri-state behaviour with multiplexers.