A question about generate pulse signal between different clock zone

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I need to generate a 124M pulse from a 52M pulse. Restrited by the pipeline stages, I use this method:

always @ ( ... posedge clk_124 )

...

sig124 <= P52;

end

always @ ( ... posedge clk_124 )

...

p124 <= P52 & (~P124);

end

I wonder if this method is safe? :D

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Hi,

what is the purpose of sig124? Should be "p124" the same signal as "P124" ?Be aware that verilog is case sensitive.