A problem with using DCFIFO (lpm_fifo)

Hello!

In my design I have a 8bit x 4 words dual-clock fifo component (LPM_FIFO+) and I observe a very strange behaviour or the wrfull output signal.

Since I have fifo 4 word-deep I expect the wrfull signal go high on a 4th write I am surprised when the wrfull goes high right after the first write cycle.

I have tried to enable all the protection circuits available in this component but still not get the good results. The fifo component is on the data input to the uart transmitter...

At this point I would appreciate a fresh pair of eyes look from somebody on the forum - maybe there is something obvious wrong and I do not see it. Can you help me?

Here is the fragment of the circuit with the fifo component:

http://s820.photobucket.com/albums/zz128/pszemol_alt/?action=view&current=fifo.jpg

And here simulation with the wrfull signal going high after first write:

http://s820.photobucket.com/albums/zz128/pszemol_alt/?action=view&current=simul.jpg

Please note, wrfull signal is visible in the simulation as TX_EMPTY and is inversed.

Any ideas where and what to check?

Thanks!