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Altera_Forum
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13 years ago

A problem of gate-level simulation of PLL dynamic phase shift in Cyclone III

Hi,

I am now doing the gate-level simulation of PLL dynamic phase shift in Cyclone III, using the interface such as phasedone, phasestep and phasecounterselect. In it, c0 and c1 are two output clocks and I expect the phase of c1 to be shifted. I generated the waveform according to the PLL manual (e.g. phasestep is asserted high for at least two cycles). However, I found the following two weird phenomena:

(1) the signal 'phasedone' only becomes low for half of the scanclk cycle and then asserted high.

(2) the phase of c1 is never shifted.

I have been trapped in this problem for more than one day and searched a lot of materials, but still not found the cause. Thanks very much for the help on the forum.

Best,

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    Based on the given information, it's hard to guess if it's a simulation problem or if you are controlling the PLL phase shift incorrectly.

    1. Can you show the complete simulation waveforms?

    2. Did you check against the behaviour in real hardware, e.g. observing the PLL control signals with SignalTap II?
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    --- Quote Start ---

    Based on the given information, it's hard to guess if it's a simulation problem or if you are controlling the PLL phase shift incorrectly.

    1. Can you show the complete simulation waveforms?

    2. Did you check against the behaviour in real hardware, e.g. observing the PLL control signals with SignalTap II?

    --- Quote End ---

    Hi,

    The simulation result is shown in the attachment. Thanks!
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    12 years ago

    Hi Dennis,

    did you find solution for the problem. I have designed a statemachine to controlle the parameters of the pll as described in the data sheet. but It seems it doesnt work. I always see value 'zero' at phasedone port .

    if you have code for statmachine or any information how pll works dynamically please help me.

    thanks and best regards,

    sarat