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Honored Contributor
Honored ContributorA problem of gate-level simulation of PLL dynamic phase shift in Cyclone III
Hi, I am now doing the gate-level simulation of PLL dynamic phase shift in Cyclone III, using the interface such as phasedone, phasestep and phasecounterselect. In it, c0 and c1 are two output ...
Altera_ForumHonored Contributor
Honored ContributorBased on the given information, it's hard to guess if it's a simulation problem or if you are controlling the PLL phase shift incorrectly.
1. Can you show the complete simulation waveforms? 2. Did you check against the behaviour in real hardware, e.g. observing the PLL control signals with SignalTap II?
