A erratic phenomenon of FIFO in FPGA

thank you very much, kaz.

i think i do at last find the problem.

it is the writing clock that causes so much exotic phenomenon, i am sorry for my careless checking this signal.

thank you again for your patience and time.

ingdxdy

p.s. in fact, i donot trust simulation much. a lot of situations such as clock jitter, precise hareware timing cannot be simulated. i like running direclty and check with signaltap.