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Honored Contributor

15 years ago

A erratic phenomenon of FIFO in FPGA

Hello, I am using megawizard to generate a fifo of 8bitsx1024words in EP3C16. An interesting result occurs, when fifo is full(wrfull=1), it at the same time indicates that there is no data to r...

Altera_Forum

Honored Contributor

15 years ago

Thats ok. I use half full just because it is easy to check using one bit logic.

I have never seen fifos behaving like what you see. I think it is best to use simulation of fifo on its own as I mentioned before.

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A erratic phenomenon of FIFO in FPGA

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