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Altera_Forum
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15 years ago

A erratic phenomenon of FIFO in FPGA

Hello, I am using megawizard to generate a fifo of 8bitsx1024words in EP3C16. An interesting result occurs, when fifo is full(wrfull=1), it at the same time indicates that there is no data to r...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

It might help to do this short exercise:

write but do not read fifo until word count = 512 (MSB = '1') then start and continue reading. 


clked process...
if fifo_words(9) = '1' then
    fifo_ready <= '1';
end if;
wr <= '1';
rd<= '1' when fifo_ready = '1' else '0';