A erratic phenomenon of FIFO in FPGA

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Optimising the operating point to the middle may waste a lot of memory, I'd rather say you optimise you system to keep fifos empty, but make them big enough to handle the bursts

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You may be thinking of using fifo just as fixed memory for block processing.

But using fifo as "elastic" buffer for continuous stream processing and especially if the stream is bursty requires naturally that there is elasticity on both sides of operating point otherwise you get empty or full fifo repeatedly losing your stream continuity.