Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorA erratic phenomenon of FIFO in FPGA
Hello, I am using megawizard to generate a fifo of 8bitsx1024words in EP3C16. An interesting result occurs, when fifo is full(wrfull=1), it at the same time indicates that there is no data to r...
Altera_ForumHonored Contributor
Honored ContributorThe strange behaviour as seen by signaltap does not make sense.
You better simulate your fifo on its own before moving to hardware.
