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Honored Contributor
Honored ContributorA erratic phenomenon of FIFO in FPGA
Hello, I am using megawizard to generate a fifo of 8bitsx1024words in EP3C16. An interesting result occurs, when fifo is full(wrfull=1), it at the same time indicates that there is no data to r...
Altera_ForumHonored Contributor
Honored ContributorHello,
There is another problem when using FIFO. when i write data into fifo, the rdusedw behaves strangely. as figure(grasped with signaltap) in the attachment shows, rdusedw(which has combined with wrfull as josyb directs) jumps to full(0x3ff) from zero disruptly when i only write 4 bytes into it. the fifo is dual port with different read and write clock. reading and writing may occur simultaneously. can anyone help me? thanks a lot.
