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Honored Contributor
Honored ContributorA erratic phenomenon of FIFO in FPGA
Hello, I am using megawizard to generate a fifo of 8bitsx1024words in EP3C16. An interesting result occurs, when fifo is full(wrfull=1), it at the same time indicates that there is no data to r...
Altera_ForumHonored Contributor
Honored ContributorFifos may show unpredictable behaviour if you write to a full one. Best practice is to optimise the operating point near the middle. If it gets full you must have logic to return back to this optimum point.
If your fifo is dc then check your reset operation.
