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Altera_Forum
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12 years ago

800MHz counter on Cyclone ?

I need a high resolution (28 bits or more) with an 800MHz clock. Is it possible to use the VCO to clock a counter if I run the PLL with a M=8 multiplier with a 100Mhz to get a VCO of 800MHz ?

4 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    You might be able to generate it, but you'll violate the setup and hold of any internal logic.

  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    Depending on what you want to achieve, multiple phase shifted clocks may be a solution. In any case, your design should be aware of the Cyclone hardware specifications.

  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    --- Quote Start ---

    Depending on what you want to achieve, multiple phase shifted clocks may be a solution. In any case, your design should be aware of the Cyclone hardware specifications.

    --- Quote End ---

    That's what I was thinking.

    Is it possible to get all 8 phase shifted outputs (45,90,135...315 deg) from a single PLL output ? If so, my thought was to feed these 8 phase shifted outputs to latch FFs with a 100MHz clock for digital interpolation. I' pretty sure this is possible in Xilinx FPGAs and was hoping to do the same on a Cylcone II,III ?

    Thanks for all the help as I come up to speed !
  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    OK, I think I've got a working solution using all 5 of the PLL outputs each with a unique phase. Now onto figuring out how to implement the interpolator.