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New Contributor5CEBA7F27C8N JTAG Interface Debugger Support
Hello,
USB Blaster UG-USB81204 is considered for Debugging Cyclone V (5CEBA7F27C8N)
1. What is the maximum TCK frequency that is supported by USB Blaster UG-USB81204
2. What will be minimum and maximum output delay on TDI and TMS lines from falling edge of TCK
3. What will be the setup and holdtime requirement of TDO line wrt to TCK rising edge of USB Blaster UG-USB81204
4. Will the debugger generate TCK signal with 50% duty cycle only?
4 Replies
FakhrulA_alteraRegular Contributor
Hi ShivaKi,
You may refer to the timing spec more detailed in the datasheet: Cyclone V Device Datasheet
regards,
Fakhrul
- ShivaKi
Hello Fakrul,
For USB Blaster Debugger also, the same timing specifications mentioned in Cyclone V datasheet will be applied? Please confirm
with regards
Shiva
FvMSuper Contributor
Hi,
the only relation between USB-Blaster and Cyclone V timing specification mentioned in previous post is that USB-Blaster surely fulfills Cyclone V requirements. That wasn't your question as far as I understand.
I tried to answer your original question in cross-posted thread https://community.intel.com/t5/FPGA-SoC-And-CPLD-Boards-And/USB-Blaster-Download-cable-Timing-Specification/m-p/1643839
Still not clear to me what you want to achieve. If you have specific questions not directly related to Cyclone V debugging, you should ask explicitely.
Regards
Frank
- FakhrulA_altera
As we haven't received a response to our previous notification, this thread will be transitioned to community support. We hope all your concerns have been addressed. If you have any new questions, please feel free to open a new thread to receive support from Intel experts. Otherwise, community users will continue to assist you here. Thank you.
