Honored ContributorHi,
I want to create a 500Khz signal 3.3v to 5-10Hz verlog divider, for a led driver. I have some experience of verlog and ideas. Is there a simpler method of debugging that using model sim(altera). Many Thanks Dave
Honored ContributorThis example should help:
http://www.alteraforum.com/forum/showthread.php?t=34391 Cheers, DaveHonored ContributorFrom 500 kHz to 10 Hz is a ratio of 50 k = 50000. So a binary up counter 16 bit will give you a ratio of 65,536. If counter output is [15..0], then MSB [15] is ok for your application. If not, make the counter 17 bit, and outputs the MSB [16] to LED.
Honored ContributorThanks Waiyung.
I am using a de1 board to test divider and will use ext skt input 500KHz. I show the basic code below, for one led channel, could you tell me if it looks correct. =================================================== module tim_counter( clk50M, // clk27M, //extclk, reset_N, ledout ); input clk50M; //output reg ledout; //input clk27M; //input extclk; input reset_N; output reg ledout; reg [15:0]counter; always @ (posedge clk50M or negedge reset_N) //always @ (posedge extclk or negedge reset_N) //always @ (posedge clk27M or negedge reset_N) begin if (!reset_N) begin counter <= 16'd0; ledout <= 1'b0; end else if (counter==16'd5000) begin counter <= 16'd0; ledout <= ~ ledout; end else begin counter <= counter +1; end end endmodule =================================================== I use a top.v file and a pll.v file together with the divider file Thanks Dave
