500 MHz On-Board Clock Oscillator

Are you aware of the built-in PLL feature of all modern FPGAs? They effectively superseed fast clock oscillators as a FPGA clock source.

In those special cases where you need a low jitter 500 MHz source, e.g. to clock a high speed ADC or DAC, you would bypass the FPGA to avoid detoriation of the clock quality.

Thank you FvM,

Could you please be more detailed as I am new in FPGA. I am using FPGA for controlling the Pulsed Power generators. What we do is modifying the pulses for example putting delay, select specific pulses and ...

I am using Cyclone IV DE0-nano board. Board's oscillator is 50 MHz and the minimum pulse period is 20 ns. I use it as my frequency source.

Could you please guide me how can I reach to 500 Mhz as a frequency source? Is there any FPGA board with 500 MHz oscillator? if I have to use PLL what are the steps? any tutorial?

Thank you very much for your help.

You can easily generate an internal clock of up to 472 MHz (the maximum PLL output frequency of Cyclone IV C6 speed grade). To achieve 500 MHz output data rate, you preferably use 250 MHz clock and dual data rate registers.

The 3.3V IO standards available with DE0-nano will hopefully achieve 500 MHz data rate respectively 250 MHz toggle rate.