Forum Discussion
Altera_Forum
Honored Contributor
12 years agoAre you aware of the built-in PLL feature of all modern FPGAs? They effectively superseed fast clock oscillators as a FPGA clock source.
In those special cases where you need a low jitter 500 MHz source, e.g. to clock a high speed ADC or DAC, you would bypass the FPGA to avoid detoriation of the clock quality.