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Altera_Forum's avatar
Altera_Forum
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9 years ago

5 Gbps USB 3.0 PIPE interface via Cyclone V GT 6 Gbps transceivers?

I'm considering using a Cyclone V GT (that has 6 Gbps transceivers) to implement a USB 3.0 protocol analyzer. The idea is to split the upstream and down stream signals (externally) and input a copy of the streams to two transceiver RX inputs on the Cyclone V GT. I have used this method successfully in the past for PCI Express protocol analysis.

My question is: Would I be able to use the Cyclone V GT transceivers in PCIe PIPE mode for USB 3.0 interception? The 8b/10b encoding is identical and the OOB signaling looks very similar?

If not, how are the transceivers configured to capture both SS data as well as OOB signaling (LFPS)?

Also, PCIe uses an external refclk of 100 MHz, while USB 3.0 does not. Could I simply provide my own that is within the PPM requirements (not to over/under flow the elastic buffer)?

I know there are USB 3.0 IP cores for Cyclone V so it should be possible to interface.

Thanks.

4 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    9 years ago

    Hi, did you ever find an answer for this question? I am interested in doing something similar and was curious about your experience.

    Thanks
  • Altera_Forum's avatar
    Altera_Forum
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    9 years ago

    No, I have not yet found a solution. I'm again looking into this design problem.

  • Altera_Forum's avatar
    Altera_Forum
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    9 years ago

    Can anyone please confirm that it is not possible to configure Cyclone V GT PIPE interface (v15) for 5 Gbps? And, if so, why not since the transceivers support up to 6 gbps? The Megawizard only allows configuration to 2500 Mbps and it compiles okay. When manually editing the IP to 5000 Mbps per below:

    altera_xcvr_pipe# (

    .device_family ("Cyclone V"),

    .lanes (1),

    .protocol_version ("Gen 2"),

    .base_data_rate ("5000 mbps"),

    .pll_type ("CMU"),

    .pll_refclk_freq ("100 MHz"),

    .deser_factor (16),

    .bypass_g3pcs_scrambler_descrambler (1),

    .bypass_g3pcs_dcbal (1),

    .pipe_run_length_violation_checking (160),

    .pipe_low_latency_syncronous_mode (0),

    .pipe_elec_idle_infer_enable ("false"),

    .mgmt_clk_in_mhz (100)

    I'll end up with the below error:

    Error: Clock Divider Parameter 'data_rate' is set to an illegal value of '5000.0 Mbps' and PMA Direct parameter is set to 'false'. If PMA Direct is false, the value is illegal for protocol mode: 'pipe_g2' with a device speed grade of '7_H5', PMA WIDTH of 'ten_bit' and byte serializer mode : 'en_bs_by_2' and latency 'dis_pcs_bypass' on atom 'Pipe0:pipe0_inst_USB_A|altera_xcvr_pipe:pipe0_inst|av_xcvr_pipe_nr:pipe_nr_inst|av_xcvr_pipe_native:transceiver_core|av_xcvr_native:inst_av_xcvr_native|av_pma:inst_av_pma|av_tx_pma:av_tx_pma|av_tx_pma_ch:tx_pma_insts[0].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb'. If PMA Direct is true, the value is illegal for PMA-PLD WIDTH of '10'.

    Is there any way to tweak things so I can get the PIPE interface to support 5 Gbps (actually USB 3.0) or would I have to drop down to a lower interface (like Native PHY)?

    Thanks.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    9 years ago

    Hi John,

    you should contact Altera support on that, if it is possible they should be able to give you a solution.

    Cheers,

    fade