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Altera_Forum
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15 years ago

3 NODES IN JTAGCONFIG -n SHOWN . How to delete one?

Hello, I'm doing altera tutorial project "hello word small"

FPGA is CycloneIII 3C25

Software Quartus II 10.1sp1 Web Edition

NIOSII EDS 10.1 sp1

Cable USB-Blaster

SOPC system consists of:

nios2

sys_id

on_chip_memory

io_port

jtag_uart

So I face a problem: download elf. file process failed. I've tried it second day. Couple of times i've downloaded the elf. file to the device and it worked correctly, but the most times errors occure: download elf. file process failed.

I tried to use command line instead of GUI but nothing changes.

The thing i've expired:

command jtagconfig -n has such results:

usb-blaster [usb-0]

020f30dd ep3c25/ep4ce22

node 19104600

node 0c006e00

node 00086e00

so I have 3 nodes - nios2, jtag uart and a third one that i can't recognize. Could you provide me with information how to remove the third one NODE 00086E00, may be it is the cause of my trouble.

Thanks from Russia.

5 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    The VJTAG node ID 00086E00 is related to an OpenCore Plus (OCP) time limited evaluation feature and can't be removed, unless you have full licenses for the IP cores used in our design.

  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Thanks for your answer, FvM.

    As I know this, this node isn't the cause of my problem. SBT for Eclipse can't find system id and system timestamp. What might cause this problem as I do everything like instuctor in altera tutorial does?
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Yes, but are you keeping the QII programmer window open after programming your FPGA image (SOF, POF) to the FPGA? This is a requirement for any IP with OCP limitations. On the FPGA, the OCP just queries the host (PC) every so often (over JTAG) and if the host isn't "there", it stops/times out the IP that is using it. I'm assuming that it's your Nios II processor that's causing this. You can downgrade to an "e" core as it has no such restrictions...if you like.

    Regards,

    slacker
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Thank you for your answer, slacker, I do not disconnect my fpga from the host pc. Tried to use /e revision of nios2, but faced the same problem. processor downloaded to the fpga do not respond, do not transfer id and timestamp data. What my cause the problem is such case??

    PS Tried at two computers windows seven 64x and windows xp 86x, but nothing changes. Have no ideas.

    Any systems without nios2 (ex. state machines) are downloaded and work corectly.

    While generating sopc system in Qii system id in 10.1sp1 is always 0 by default (timestamp is't zero equal). Is it correct?
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    I'm not sure...check clock, reset, memory interfaces, etc. For a first program, I would try creating something very small that will fit in a small (16K or less) onchip memory. No offchip memory...to start with.

    Also, when you do a "jtagconfig -n" with the E core, do you see only two nodes? If Nios II/s or f were the cause of the OCP, then that should be the case.

    Regards,

    slacker