Forum Discussion
Altera_Forum
Honored Contributor
15 years agoYes, but are you keeping the QII programmer window open after programming your FPGA image (SOF, POF) to the FPGA? This is a requirement for any IP with OCP limitations. On the FPGA, the OCP just queries the host (PC) every so often (over JTAG) and if the host isn't "there", it stops/times out the IP that is using it. I'm assuming that it's your Nios II processor that's causing this. You can downgrade to an "e" core as it has no such restrictions...if you like.
Regards, slacker