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Altera_Forum
Honored Contributor
Honored Contributor3.3V clock input on ddr3 i/o bank
Hi
I have a board with a cyclone v (5CEFA2F23C8) and a ddr3 ram. On the same I/O-bank 7A as the ddr3 I have a clock input, as needed for running the ddr3-pll. My problem is, the pll does not lock! Could it be that I have a 3.3V signal for my dedicated clock input? I thought that the 1.5V i/o bank can work with this higher voltage on a input. Do I have to configure my clock input pin specially? Thanks for any help3 Replies
Altera_ForumIf the bank is a 1.5 IO bank, you need to drive it with a 1.5V signal. Anything higher will potentially burn out the IO pin and will over load the driving chip.
- Altera_Forum
Quartus won't let you do this. So, I suspect you've not specified the I/O standard of your clock input signal. Quartus will moan with a message such as:
--- Quote Start --- Pin uses I/O standard 3.3-V LVCMOS, which has a VCCIO requirement incompatible with that bank's VCCIO setting or its other pins that use VCCIO 1.5V. --- Quote End --- You'll need to change your clock signal to a 1.8V I/O standard or lower to drive into a 1.5V powered bank. This is detailed in the I/O Standard Specifications section, page 17, of the cyclone v device datasheet (https://www.altera.com/en_us/pdfs/literature/hb/cyclone-v/cv_51002.pdf). Cheers, Alex - Altera_Forum
Thanks for the link alex. Now it makes sense, one board was working and my second board didn't. I had in my mind, that cyclone IOs would tolerate higher voltages when they are inputs. I will place a voltage divider in between.
