Forum Discussion
Altera_Forum
Honored Contributor
Honored Contributor27 MHz from 50 or 125 MHz?
Hello all, I am working on a project in which I need a 27MHz clock for the VGA interface. I am using Cyclone III 3c120 FPGA and it has only 50MHz and 125MHz oscillators. Can I get 27M...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- Use an ALTPLL mega-function with an input clock of 50MHz and an output clock of 27MHz, it wouldn't of thought it would have a problem achieving that. --- Quote End --- Thanks. I tried that already before posting my question. I got the error message "Cannot implement the requested PLL. Cause: Requested mult/div factors not achievable." Instead it generated 27.083333 MHz clock. I wanted to know if I can generate exact 27MHz clock.
