New ContributorWe re trying to enable 200Mhz single ended IO. Would like to seek some technical support on how to enable this. On the same topic, what is the risk of running with 200MHz on a large qty of FPGAs. Will there be a risk due to binning issue?
And is there a recommended drop in upgradable parts from our current FPGA, 5SGXMA3K3F40C4, to another with capability of clock speed up to 400MHz
Frequent ContributorWe re trying to enable 200Mhz single ended IO. Would like to seek some technical support on how to enable this.
==> Enable as input or output?
On the same topic, what is the risk of running with 200MHz on a large qty of FPGAs. Will there be a risk due to binning issue?
==> On all IO pins? How many FPGAs? How do you connect? Is there any diagram?
==> Can you give me some background? what is your end goal?
==> Can you elaborate on "risk due to binning issue"?
And is there a recommended drop in upgradable parts from our current FPGA, 5SGXMA3K3F40C4, to another with capability of clock speed up to 400MHz
==> Can you elaborate the background more, then perhaps I can help from a better perspective.
