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Altera_Forum's avatar
Altera_Forum
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15 years ago

2 stages boot loader

Hi

I'm trying to fit a design that requires a boot loader into a small FPGA, but there is not enough space for both of them.

so I had an idea, why not use 2 designs:

boot loader design fills up the external RAM, and tells the host when it is done.

then the host override the boot loader design and loads the "operational" design.

the operational design NIOS has the external RAM for reset and exception vectors.

before I dive into it and push around the SW team, I would appreciate everyone thoughts and ideas for possible mines, draw backs and better alternatives.

thanks in advance

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    Hi

    luckily I'm using SRAM. so I don't have to worry about refresh cycles and so on.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    Do you use SRAM or SDRAM?

    If SDRAM, does it have Auto-refresh?

    If not, there's a risk your contents might get corrupted during reconfiguration.

    What time would reconfiguration take?