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Altera_Forum's avatar
Altera_Forum
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14 years ago

2.6GHz serial IO without transceiver

Hello, I'm working in a project that using FPGA and high speed comparator to acquire external signals. In the design, the comparator acquire data and translate to PECL logic( equal or less t...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

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Is there any method to make the FPGA interface with 2.6GHz serial data without Transceiver or make the Transceiver acquire data simultaneously?

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Your problem description isn't very detailed. I understand, that you mean to actuslly sample data at a rate of 2.6Gbps? In this case, the first variant can be excluded, unless you are using external SERDES hardware, e.g. an ECL shift register. For the second variant, did you check if your FPGA is able to read raw serial data with it's Gigabit transceivers? Some FPGA families are rather restricted in this regard, e.g. limited to DC balanced bit streams.