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Altera_Forum's avatar
Altera_Forum
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15 years ago

2.6GHz serial IO without transceiver

Hello, I'm working in a project that using FPGA and high speed comparator to acquire external signals. In the design, the comparator acquire data and translate to PECL logic( equal or less t...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Thank you for your reply!

I think your method maybe applicable. I can use the presudo bits to allign the receiver first, and then store the data after the trigger and drop the data befor the trigger.