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Altera_Forum
Honored Contributor
Honored Contributor16Bit YCbCr video port
Dear Altera-Team, we want to convert 16Bit wide YCbCr data comming from our camera to fit to our 8Bit wide camera interface. The idea is to use a CPLD to buffer the 16Bit data and send it out i...
Altera_ForumHonored Contributor
Honored ContributorHi,
I just did a really naive implementation in Quartus and it met timing requirements with no effort. I don't see your requirement for 300 MHz operation. What you do need to watch out for is delays between your 74.25 MHz clock and your 148.5 MHz clock. Presumably one is generated from the other so they are always an exact multiple of 2, but delays through a PLL or PCB tracking could change their relative phase enough to break things. You can specify the delays in TimeQuest to make sure it really does meet the timing requirements of your real board. Mark.
