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Altera_Forum
Honored Contributor
17 years ago16-bit 4 inputs interfacing with 16-bit 1 input of DCFIFO
hi, i'm thinking to interface these 16-bit 4 inputs to 16-bit 1 input of DCFIFO. i want the data to be written in sequence, starting from Q1 to Q4. when wrreq is asserted in DCFIFO, the output...
Altera_Forum
Honored Contributor
17 years agook. need to study this code. normally, i create separate code for datapath and control unit.
by the way, why should i need two different clocks? fulldataclk and fifoclk? can i just use the same clock? thanks