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Altera_Forum
Honored Contributor
17 years ago16-bit 4 inputs interfacing with 16-bit 1 input of DCFIFO
hi, i'm thinking to interface these 16-bit 4 inputs to 16-bit 1 input of DCFIFO. i want the data to be written in sequence, starting from Q1 to Q4. when wrreq is asserted in DCFIFO, the output...
Altera_Forum
Honored Contributor
17 years agothe verilog file that i have sent to you contains both the 4to1 mux so as the control unit, even if it's not explicit. i've done a simulation test to the file inter4to1.v and the logic is working as expected, see a screen shot of the modelsim simulation in attachment ...