Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

10M50DA clock frequency PLL in EPE

Hi ALTERA-forum, I am new to the FPGA design and now want to start with the EPE. Now I have two problems. One with the frequencies and another with the dissipation. 1. I want to use the...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

Hi Bob,

thank you for your reply.

I checked the links and have to say thank you. The first one i knew but I must have missed the second one.

The data for the power rails are quite common with my calculated data. I will only use LVCMOS signals and probably DDR3 Flash so my expected current for some rails wont be this much.

Thank you very much!

Best regards.

Jérôme