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Altera_Forum
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9 years ago

10M50DA clock frequency PLL in EPE

Hi ALTERA-forum, I am new to the FPGA design and now want to start with the EPE. Now I have two problems. One with the frequencies and another with the dissipation. 1. I want to use the...
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Altera_Forum
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9 years ago

Hi Bob,

thank you for the reply.

I found this information too, but was a bit unsure about the Clock max frequency, because, as you said the datasheet shows a maximum frequency of 472.5MHz but the spreadsheet shows 600MHz.

In case of the max power for the MAX10 device I don't just maxing out the parameters. I looking up for the signals the FPGA will working with and their voltage level and operating frequencies. Then I put a little margin on the frequency.

The data to the Dev Kit is looking interesting.

The Power tree looks quite similar to mine. Instead of the 12V to 5V I am using 24V to 3.3V. I dont want to use FTDI or HDMI, so I think I am fine by using the 3.3V directly converted from teh 12V. I just have to look for the current ranking. 3.3V @ 3A will do fine. There are just VCCIO and SPI on this rail.

Thank your for the links. They help me alot.

Best Regards

Jérôme