Honored Contributor
Honored ContributorSee Table 27 in the MAX 10 datasheet for the PLL specs:
https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/hb/max-10/m10_datasheet.pdf According to this data sheet the max VCO frequency is 1300MHz and the max output clock frequency is 472.5MHz for the fastest speed grade. However, Table 26 for the clock tree specs says the max clock frequency is 450MHz. So that's realistically your limit. There are lower frequency limits for things like embedded multipliers and block RAMs. All of the information is in the data sheet. I can't speak to the max power a MAX 10 device can use. If you're trying to estimate currents so you can pick power supplies a good reference point would be to look at the schematic and BOM for MAX 10 development kits and see what regulators were used on those. If you're concerned about heat removal for thermal management then you'll have to try to come up with a more realistic worst case for your design rather than just maxing out everything in the EPE spreadsheet. The MAX 10 dev kit from Altera uses the 10M50D, so that should be a good reference point: https://www.altera.com/products/boards_and_kits/dev-kits/altera/max-10-fpga-development-kit.html You can download the schematic and BOM from this page. By the way, your English is excellent! Bob
