New Contributor
New ContributorI've already tried setting "Toggle Rate" to "0 MHz" on both adjacent output pins 28 and 30 adjacant of PLL clock input pin (CLK_50M) in pin location 29 with different "Current Strengt" and "Slew Rate" settings without any success so far.
Also, Quartus does not seem to allow the User to Suppress Error Message (18496).
It seems like Intel simply do not allow override of their Signal Integrity Design Guidelines for the Clock Input Signal:
This is just fine, that is until you realize each and every single pin of the 144pins in your hardware design has already been spoken for.
So maybe my best and only option right now is to have my FPGA designer work on this problem using an older version of Quartus with its "preliminary timing models" even though this is far from optimal.
If Intel allowed to Suppress Error Message (18496) we could instead work on this problem using the latest Quartus version.
