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2reSolve's avatar
2reSolve
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2 years ago

10M08SCE144C8G Temperature Issues

Hi, We're having some wird temperature issues with some newer 10M08SCE144C8G FPGA chips date marked with "2301A". The FPGA chips are used in an older MUX design "which have always worked before". ...
Board Debug
2reSolve's avatar
2reSolve
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10 months ago

Buying the FPGA chips from authorized distributor this time did not solve this issue.

Also, after hiring an FPGA expert for reviewing our FPGA design we are informed the project does not build because of Error (18496): The Output TLK_TX[1] in pin location 28 (pad_1628) is too close to PLL clock input pin (CLK_50M) in pin location 29 (pad_1)

This errror was not present (even as a warning) when the project was originally build with Quartus II 15.0.2.153 back in 2015.

So please, is there "a work around" for Error (18496) which allows this project to build with the newer Quartus versions?

FvM's avatar
FvM
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10 months ago
Yes there's a simple workaround by assigning toggle rate of "0 MHz" to pin 28 in pin planner or assignment editor to suppress distance rule application. It however depends on output signal characteristic if it can be done without causing signal integrity issues.