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Altera_Forum
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9 years ago

10M02DCV36I7G - cheap, reliable clocking

I am new to MAX10s and pretty new to FPGAs in general, and will be using 10M02DCV36I7G as a peak detector. The inputs come from two single-ended comparator outputs. I plan to use a number of ph...
Altera_Forum's avatar
Altera_Forum
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9 years ago

If you have the luxury of making repetitive measurements on the same signal, then you could dynamically shift the phase of the PLL (rather than using multiple phase-shifted outputs) and average multiple readings to reduce the effects of random jitter.