Hello Dave, thank you for your reply.
I need to use 4 clock inputs. To use the 4 pll's.
I have to confirm that the dedicated clock pins can be LVDS or not. I prefer to use dedicated input clock signals not emulated.
In the documentation it is not clear that the LVDS input buffers are dedicated or not.
The device (Cyclone III) documentation refers to dedicated lvds transmitters placed at 1, 2 5 and 6 IO Banks.
The reason of my confusion is that in the same documentation (Cyclone III Device Handbook Volume 1 page 6-20) says and I quote "The LVDS standard does not require an input reference voltage, but it does require a 100-Ωtermination resistor between the two signals at the input buffer. An external resistor network is required on the transmitter side for top and bottom I/O banks."
However in Cyclone III Device Handbook Volume 1 page 6-13 says in Note 8 of Table 6–4: "True differential LVDS, RSDS, and mini-LVDSI/O standards are supported in left and right I/O pins while emulated differential LVDS(LVDS_E_3R), RSDS(RSDS_E_3R), and mini-LVDS(LVDS_E_3R) I/O standards are supported in both left and right, and top and bottom I/O pins."
So, do all the IO banks have dedicated LVDS receivers only requiring a 100-Ωtermination resistor or should I consider that dedicated LVDS I/O standards are ONLY supported in both left and right, and top and bottom I/O pins.
This indicates if I need to change my board layout or not.
Regards
Miguel
Honored Contributor
