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Altera_Forum's avatar
Altera_Forum
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10 years ago

1.8V LVDS inputs

Hello,

I am using a Cyclone IV EP4CE15 FPGA and I need to accept 1.8V LVDS inputs from an image sensor. (100R termination, 150mV voltage swing, 0.9V common mode voltage).

I am unsure how to do this.

  1. I don't think it is as simple as just selecting LVDS inputs and driving the VCCIO of that bank at 1.8V?

  2. It seems I should use SSTL as the input and drive the VCCIO with 1.8V and the VREF with 0.9V. But then I can only use the dedicated clock input pins (2/bank)? I have 5 channels to accept so 2/3rds of the I/O must then be at 1.8V?

  3. If I do this the termination will be wrong with those banks that have on-chip termination (I require 100R differential termination)?

Can someone help to clarify the above please? Or is it easier to use external LVDS to single ended receivers?

Daniel.

6 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    The VCCIO voltage for a bank with LVDS inputs on the Cyclone IV MUST be 2.5V (look in the device handbook). The LVDS inputs will be compatible with your image sensor. No VREF voltage is required. The I/O type must be specified as LVDS in the Quartus Pin Planner. There is no OCT for LVDS inputs, you must supply an external termination resistor.

  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    --- Quote Start ---

    The VCCIO voltage for a bank with LVDS inputs on the Cyclone IV MUST be 2.5V (look in the device handbook). The LVDS inputs will be compatible with your image sensor. No VREF voltage is required. The I/O type must be specified as LVDS in the Quartus Pin Planner. There is no OCT for LVDS inputs, you must supply an external termination resistor.

    --- Quote End ---

    Thank-you for your reply. However the sensor LVDS outputs are 1.8V, not 2.5V, so I don't believe I can use the LVDS mode.
  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    As gj_leeson said, you can run VCCIO at 2.5V and use LVDS inputs. The LVDS outputs from the 1.8V sensor will be compatible with the LVDS inputs in the Cyclone IV 2.5V bank. Check the data sheets (sensor and Cyclone IV) to verify this for yourself.

  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    I understand what you are saying. As long as the amplitude of the LVDS signal are the same then the Cyclone LVDS receivers will operate. But as the common mode voltages are different (0.9V against 1.25V) would I not have to AC couple the LVDS inputs?

  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    Are you sure the common mode voltage out of the sensor is 0.9V? Table 1-20 in the Cyclone IV data sheet gives the LVDS specs. If your data rate is < 700Mbps then a common mode voltage (Vicm in the table) of 0.55V to 1.80V is allowed. If your data rate is > 700Mbps then 0.9V is out of range.

  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    Yes, 0.9V. Part of today's trend to invent your own standards rather use established ones. My data rate is not so high, and the LVDS amplitude is high enough, so I think it means I can just DC couple the inputs into the FPGA (using LVDS inputs at VCCIO of 2.5V). I guess there is one way to find out.

    Thanks everyone.