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Altera_Forum
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8 years ago

1.8V HSTL Differential DDR output using ALTDDIO_OUT on Cyclone 10 LP

I need to drive multiple 1.8V HSTL differential pairs from a Cyclone 10 LP FPGA. The output is DDR, source synchronous. I am currently doing this with single-ended signals using the ALTDDIO_...
Altera_Forum's avatar
Altera_Forum
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8 years ago

Sorry for the original question being confusing. My basic question is how can I use the DDR output registers (thru ALTDDIO_OUT) to drive two pins in a pseudo-differential fashion (one inverted from the other)? What is the suggested approach? I don't think we can invert the output of the ALTDDIO for the negative pin.

Specifically, I'm targeting a Cyclone 10 LP FPGA, with VHDL using Quartus Prime v17.1.