Altera_Forum
Honored Contributor
Honored Contributor# - Time Delay
So i understand the# is used as a delay, however
-What clock does it use as reference to delay? -Is this only for simulation? Does it have no effect on an actual FPGA?Forum Discussion
3 Replies
Altera_ForumIt is only for simulation indeed.
No effect on real design. Use it in a procedural block of a testbench. It will delay one instruction from the subsequent. As a consequence there's no 'reference' clock. The delay is from one instrction to the following.- Altera_Forum
If you put
at the start of your test bench file, the period defined by the# delay is then in nanoseconds. i.e.# 100 is 100ns.`timescale 1 ns / 100 ps - Altera_Forum
(http://www.alteraforum.com/forum/newreply.php?do=newreply&noquote=1&p=104561)good point
thank you
