Altera_Forum
Honored Contributor
Honored Contributor# - Time Delay
So i understand the# is used as a delay, however -What clock does it use as reference to delay? -Is this only for simulation? Does it have no effect on an actual FPGA?
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Altera_ForumHonored Contributor
Honored ContributorIt is only for simulation indeed.
No effect on real design. Use it in a procedural block of a testbench. It will delay one instruction from the subsequent. As a consequence there's no 'reference' clock. The delay is from one instrction to the following.
