Hey, i'm trying to write and read to/from the sram with a cyclone3 fpga on a NEEK. I wrote a little code to check if it's working, but it doesn't and i tried very much around but to no avail. The clk input is driven by a pll with 100Mhz (of course i connected the SRAM_clk to it). I changed the configuration scheme to passive serial to use DATA[0] and DATA[1] as regular IO-pins. So here's the code, maybe someone will notice a mistake i haven't come across. library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity videosync is port (clk, nRst: in std_logic; data: inout std_logic_vector(31 downto 0); addr: out std_logic_vector(20 downto 0); nCS, nOE, nWE: out std_logic; nadsc, nbe0, nbe1, nbe2, nbe3: out std_logic; led0, led1, led2, led3: out std_logic; flashnOE, flashnCE: out std_logic); end entity videosync; architecture behave of videosync is -- readram signals type ramState is (write, read); signal ramst : ramState; signal ramcount: integer := 0; signal notWE: std_logic; signal memoryData: std_logic_vector(31 downto 0); begin readram_process: process (clk, nRst) is begin if nRst = '0' then flashnOE <= '1'; flashnCE <= '1'; nadsc <= '1'; nbe0 <= '1'; nbe1 <= '1'; nbe2 <= '1'; nbe3 <= '1'; led0 <= '1'; led1 <= '1'; led2 <= '1'; led3 <= '1'; nCS <= '0'; nOE <= '1'; notWE <= '1'; addr <= (others => '0'); memoryData <= (others => '0'); ramcount <= 0; ramst <= write; elsif rising_edge(clk) then case ramst is when write => if ramcount = 0 then addr <= std_logic_vector(to_unsigned(ramcount, 21)); memoryData <= "11111111000000000000000000000000"; nadsc <= '0'; ramcount <= ramcount + 1; elsif ramcount = 1 then notWE <= '0'; nadsc <= '1'; ramcount <= ramcount + 1; elsif ramcount = 2 then notWE <= '1'; addr <= (others => '0'); ramcount <= ramcount + 1; else ramcount <= 0; ramst <= read; end if; when read => if ramcount = 0 then addr <= std_logic_vector(to_unsigned(0, 21)); nadsc <= '0'; ramcount <= ramcount + 1; elsif ramcount = 1 then nOE <= '0'; nadsc <= '1'; if data = "11111111000000000000000000000000" then led0 <= '0'; else led0 <= '1'; end if; ramcount <= ramcount + 1; elsif ramcount = 2 then if data = "11111111000000000000000000000000" then led1 <= '0'; else led1 <= '1'; end if; ramcount <= ramcount + 1; elsif ramcount = 3 then if data = "11111111000000000000000000000000" then led2 <= '0'; else led2 <= '1'; end if; ramcount <= ramcount + 1; nadsc <= '1'; addr <= (others => '0'); nOE <= '1'; else null; end if; end case; end if; end process readram_process; nWE <= '0' when notWE = '0' else '1'; data <= memoryData when notWE = '0' else (others => 'Z'); end architecture behave; Thanks for your help, trigit. P.S. I don't know when exactly the data should arrive on the bus, so i checked some clock cycles for it with the different LEDs. But none of them is flashing :(

What is your clock frequency? The SDRAM is quite slow. Check for the datasheet but I think that the read latency is something like 80ns. Second, you don't have any connection between your memoryData signal and your data vector. To handle the bidirectionnal bus, you should have something like this outside of the process: data <= memoryData;Then to write something on the bus, write it to memoryData, as you did. But to read, first you must set the bus in a tristate mode: memoryData <= (others => 'Z'); and then read the data from data (not from memoryData!). I haven't looked at everything, but it sooks like your notWE signal isn't connected to anything either. You are also directly assigning values to some output ports in the process, and I'm not sure it would work as expected. Are you using VHDL 2008? Because if you don't it should have generated an error. Instead of using LEDs, you could use SignalTAP. It would let you see all the signals, and it is easier to check that everything works as expected.

Thank you for your reply Daixiwen, but i think you didn't read everything. First of all i'm talking about the SSRAM not the SDRAM, second as i already posted the clock frequency is 100Mhz and third, please have a look at the end of my code: nWE <= '0' when notWE = '0' else '1'; data <= memoryData when notWE = '0' else (others => 'Z'); Quartus II says i'm using VHDL 1993, should i change that? What do you mean by i am directly assigning values to some output ports? Are you talking about the control signals? And why shouldn't it work then? I will look up how to use SignalTAP, but i would be very grateful, if you'll have a look again and then maybe can help me :) Best regards, trigit

Sorry about that, I don't understand how I missed it... Better not to answer anything before my morning coffee ;) You are right, you have the correct lines. But I still think you are missing output buffers for the other control signals, including nCS, nOE, nadsc. I thought the synthesizer wouldn't allow you to do that, especially if you are using VHDL 1993 For the SRAM, I thought that this kit used the same one than on the Cyclone III 3C120 development board (that I'm more familiar with, and that uses a 'false' SSRAM). I think you still have a 2 cycles latency to read data. SignalTap isn't that difficult to learn, and it is a very very useful tool to debug any design. Spend a few hours now to learn to use it now, and you'll spare lots of hours of debugging later ;)

I didn't reply to your other question about buffers. In VHDL1993 you aren't allowed to read back the value of an 'out' port. This is a problem for registered outputs, because to maintain the value of a register between clock cycles, you need to be able to read it back. That's why I thought that the synthesizer would reject your code. There are two usual ways to fix that:[list][*]declare the port as 'buffer' instead. 'buffer' is like 'out', but allows a read feedback for registers. The problem is that if that signal is connected to another output port on the higher level component, it needs to be declared 'buffer' too instead of 'out'. That's why I call 'buffer' a viral port type, that needs to be propagated along all the hierarchy. I usually advise against it.[*]use a signal as temporary buffer, like you did on the nWE signal. This unnecessarily complicates the code, but lets you keep the 'out' port type[/list] This has been considered for a long time as one of the most stupid restrictions of VHDL. There has been a few changes to reduce this problem: in VHDL 2002, you can wire a 'buffer' port from a component to an 'out' port in an entity, removing the 'viral' constrain. In VHDL 2008, you can read back an 'out' port, removing the need for 'buffer' Most people stick to VHDL 1993 though, for the sake of compatibility. According to Murphy's law, the day you switch to VHDL 2008, you'll need to use an old tool that only understands VHDL 1993 ;). I also have some customers that require VHDL 1993, so just to be sure I won't have to rewrite everything one day, I still stick to that old standard.

Hmm... I figured out how to use SignalTap, but i don't get, why SRAM_clk is always '1'. I connected it to the PLL and its Pin is A2, but it just doesn't change?! Any idea what could go wrong? I also added the clk from the videosync inst and it doesn't change either. The other pins are changing though like expected except for the data pins... I am very confused now :|

Altera_Forum

Honored Contributor

15 years ago

writing/reading sram with cyclone3 in vhdl

Hey,

i'm trying to write and read to/from the sram with a cyclone3 fpga on a NEEK. I wrote a little code to check if it's working, but it doesn't and i tried very much around but to no avail. The clk input is driven by a pll with 100Mhz (of course i connected the SRAM_clk to it). I changed the configuration scheme to passive serial to use DATA[0] and DATA[1] as regular IO-pins. So here's the code, maybe someone will notice a mistake i haven't come across.

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity videosync is
port (clk, nRst: in std_logic;
      data: inout std_logic_vector(31 downto 0);
    addr: out std_logic_vector(20 downto 0);
    nCS, nOE, nWE: out std_logic;
    nadsc, nbe0, nbe1, nbe2, nbe3: out std_logic;
    led0, led1, led2, led3: out std_logic;
    flashnOE, flashnCE: out std_logic);
end entity videosync;
architecture behave of videosync is
-- readram signals
  type ramState is (write, read);
  signal ramst : ramState;
  signal ramcount: integer := 0;
  signal notWE: std_logic;
  signal memoryData: std_logic_vector(31 downto 0);
  
begin
  
  readram_process: process (clk, nRst) is
  begin
  if nRst = '0' then
     flashnOE <= '1';
     flashnCE <= '1';
    nadsc <= '1';
    nbe0 <= '1';
    nbe1 <= '1';
    nbe2 <= '1';
    nbe3 <= '1';
     led0 <= '1';
    led1 <= '1';
    led2 <= '1';
    led3 <= '1';
    nCS <= '0';
    nOE <= '1';
    notWE <= '1';
    addr <= (others => '0');
     memoryData <= (others => '0');
    ramcount <= 0;
    ramst <= write;
  elsif rising_edge(clk) then
    case ramst is
    
    when write =>
        if ramcount = 0 then
            addr <= std_logic_vector(to_unsigned(ramcount, 21));
            memoryData <= "11111111000000000000000000000000";
            nadsc <= '0';
            ramcount <= ramcount + 1;
        elsif ramcount = 1 then
            notWE <= '0';
            nadsc <= '1';
            ramcount <= ramcount + 1;
        elsif ramcount = 2 then
            notWE <= '1';
            addr <= (others => '0');
            ramcount <= ramcount + 1;
        else
            ramcount <= 0;
            ramst <= read;
        end if;
    when read =>
            if ramcount = 0 then
                  addr <= std_logic_vector(to_unsigned(0, 21));
                nadsc <= '0';
                ramcount <= ramcount + 1;
            elsif ramcount = 1 then
                nOE <= '0';
                nadsc <= '1';
                if data = "11111111000000000000000000000000" then
                    led0 <= '0';
                else
                    led0 <= '1';
                end if;
                ramcount <= ramcount + 1;
            elsif ramcount = 2 then
                if data = "11111111000000000000000000000000" then
                    led1 <= '0';
                else
                    led1 <= '1';
                end if;
                ramcount <= ramcount + 1;
            elsif ramcount = 3 then
                if data = "11111111000000000000000000000000" then
                    led2 <= '0';
                else
                    led2 <= '1';
                end if;
                ramcount <= ramcount + 1;
                nadsc <= '1';
                addr <= (others => '0');
                nOE <= '1';
            else
                null;
            end if;
    end case;
  end if;
  end process readram_process;
  
 nWE <= '0' when notWE = '0' else '1';
 data    <= memoryData when notWE = '0' else (others => 'Z');
end architecture behave;

Thanks for your help, trigit.

P.S. I don't know when exactly the data should arrive on the bus, so i checked some clock cycles for it with the different LEDs. But none of them is flashing :(

24 Replies

Altera_Forum

Honored Contributor

15 years ago

Well, have a look at it. (Please be sure to look at the last lines too!)

I also posted my top-level design and the SignalTap view.

I orientated my code at this one:

http://alteraforums.net/forum/showpost.php?p=12636&postcount=9

but it still won't work.

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity videosync is
port (clk, testclk, nRst: in std_logic;
      data: inout std_logic_vector(31 downto 0);
    addr: out std_logic_vector(20 downto 0);
    nCS, nOE, nWE: out std_logic;
    nadsc, nbe0, nbe1, nbe2, nbe3: out std_logic;
    led0, led1, led2, led3: out std_logic;
    flashnOE, flashnCE: out std_logic);
end entity videosync;
architecture behave of videosync is
-- readram signals
  type ramState is (write, read);
  signal ramst : ramState;
  signal ramcount: integer := 0;
  signal notWE: std_logic;
  signal notOE: std_logic;
  signal memoryData: std_logic_vector(31 downto 0);
  signal memoryAddr: std_logic_vector(20 downto 0);
  
begin
  
  readram_process: process (clk, nRst) is
  begin
  if nRst = '0' then
     flashnOE <= '1';
     flashnCE <= '1';
    nadsc <= '1';
    led0 <= '1';
    led1 <= '1';
    led2 <= '1';
    led3 <= '1';
     notOE <= '1';
    notWE <= '1';
    memoryAddr <= (others => '0');
    memoryData <= (others => '0');
    ramcount <= 0;
    ramst <= write;
  elsif rising_edge(clk) then
    case ramst is
    
    when write =>
        if ramcount = 0 then
            memoryAddr <= std_logic_vector(to_unsigned(0, 21));
            memoryData <= "11111111000000000000000000000000";
            ramcount <= ramcount + 1;
        elsif ramcount = 1 then
            nadsc <= '0';
                notWE <= '0';
            ramcount <= ramcount + 1;
        elsif ramcount = 2 then
                notWE <= '1';
                nadsc <= '1';
            ramcount <= ramcount + 1;
        elsif ramcount = 3 then
                memoryAddr <= std_logic_vector(to_unsigned(1, 21));
                memoryData <= "00000000111111110000000000000000";
            ramcount <= ramcount + 1;
          elsif ramcount = 4 then                
                nadsc <= '0';
                notWE <= '0';
                ramcount <= ramcount + 1;
          elsif ramcount = 5 then
                notWE <= '1';
                nadsc <= '1';
                data <= (others => 'Z');
                ramcount <= ramcount + 1;
          else
            ramcount <= 0;
            ramst <= read;
        end if;
    when read =>
            if ramcount = 0 then
                     notOE <= '0';
                     memoryAddr <= std_logic_vector(to_unsigned(0, 21));
                ramcount <= ramcount + 1;
            elsif ramcount = 1 then
                nadsc <= '0';
                if data = "11111111000000000000000000000000" then
                    led0 <= '0';
                else
                    led0 <= '1';
                end if;
                ramcount <= ramcount + 1;
            elsif ramcount = 2 then
                if data = "11111111000000000000000000000000" then
                    led1 <= '0';
                else
                    led1 <= '1';
                end if;
                ramcount <= ramcount + 1;
            elsif ramcount = 3 then
                if data = "11111111000000000000000000000000" then
                    led0 <= '0';
                else
                    led0 <= '1';
                end if;
                ramcount <= ramcount + 1;
                elsif ramcount = 4 then
                if data = "11111111000000000000000000000000" then
                    led1 <= '0';
                else
                    led1 <= '1';
                end if;
                ramcount <= ramcount + 1;
                elsif ramcount = 5 then
                     memoryAddr <= std_logic_vector(to_unsigned(1, 21));
                     if data = "00000000111111110000000000000000" then
                    led2 <= '0';
                else
                    led2 <= '1';
                end if;
                     ramcount <= ramcount + 1;
                elsif ramcount = 6 then
                     if data = "00000000111111110000000000000000" then
                    led3 <= '0';
                else
                    led3 <= '1';
                end if;
                     ramcount <= ramcount + 1;
                elsif ramcount = 7 then
                     if data = "00000000111111110000000000000000" then
                    led2 <= '0';
                else
                    led2 <= '1';
                end if;
                     ramcount <= ramcount + 1;
                elsif ramcount = 8 then
                     if data = "00000000111111110000000000000000" then
                    led3 <= '0';
                else
                    led3 <= '1';
                     end if;
                     ramcount <= ramcount + 1;
                elsif ramcount = 9 then
                     nadsc <= '1';
                     notOE <= '1';
            else
                null;
            end if;
    end case;
  end if;
  end process readram_process;
  
 nWE <= '0' when notWE = '0' else '1';
 nOE <= '0' when notOE = '0' else '1';
 nCS <= '0' when notWE = '0' xor notOE = '0' else '1';
 data <= memoryData when notWE = '0' else (others => 'Z');
 nbe0 <= '0' when notWE = '0' else '1';
 nbe1 <= '0' when notWE = '0' else '1';
 nbe2 <= '0' when notWE = '0' else '1';
 nbe3 <= '0' when notWE = '0' else '1';
 addr <= memoryAddr;
end architecture behave;

multiple-attachments.zip91 KB

Altera_Forum
Honored Contributor
15 years ago
I think that the first thing to investigate is why SRAM_DATA and memorydata are different when you write.
Could you move the
flashnOE <= '1'; flashnCE <= '1';
lines outside of the process? Just to be sure the flash is disabled at all times...
Did you compare the pin numbers between the board schematic and the pin planner in your project?
Altera_Forum
Honored Contributor
15 years ago
OK, i put them outside of the process.
Yeah, i checked the pin numbers several times, also in comparison to other projects provided by altera.
Altera_Forum
Honored Contributor
15 years ago
Does anyone know, where i can download the cyclone III starter kit control panel? Maybe i could look if any data is written or put some data in it and try to read it separately. I got the board from my university just for my project and didn't get the CD or anything else for it. I tried downloading the CD contents from Terasic but the control panel is not part of it there.

EDIT: ah, just found it myself on alteras ftp server.

Forum Discussion

writing/reading sram with cyclone3 in vhdl

24 Replies

Recent Discussions

DK-DEV-AGI027RBES missing device selection

SyncE clock as the reference for DDR, HBM, and FPGA control interfaces in the Agilex M-Series design

DK-DEV-AGI027RES Install Package

Cyclone V GT Dev Kit - new units fail to boot from FPP

Why 390.625MHz clock to F-Tile Reference fequency