writing/reading sram with cyclone3 in vhdl

Well, have a look at it. (Please be sure to look at the last lines too!)

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity videosync is
port (clk, testclk, nRst: in std_logic;
      data: inout std_logic_vector(31 downto 0);
    addr: out std_logic_vector(20 downto 0);
    nCS, nOE, nWE: out std_logic;
    nadsc, nbe0, nbe1, nbe2, nbe3: out std_logic;
    led0, led1, led2, led3: out std_logic;
    flashnOE, flashnCE: out std_logic);
end entity videosync;
architecture behave of videosync is
-- readram signals
  type ramState is (write, read);
  signal ramst : ramState;
  signal ramcount: integer := 0;
  signal notWE: std_logic;
  signal notOE: std_logic;
  signal memoryData: std_logic_vector(31 downto 0);
  signal memoryAddr: std_logic_vector(20 downto 0);
  
begin
  
  readram_process: process (clk, nRst) is
  begin
  if nRst = '0' then
     flashnOE <= '1';
     flashnCE <= '1';
    nadsc <= '1';
    led0 <= '1';
    led1 <= '1';
    led2 <= '1';
    led3 <= '1';
     notOE <= '1';
    notWE <= '1';
    memoryAddr <= (others => '0');
    memoryData <= (others => '0');
    ramcount <= 0;
    ramst <= write;
  elsif rising_edge(clk) then
    case ramst is
    
    when write =>
        if ramcount = 0 then
            memoryAddr <= std_logic_vector(to_unsigned(0, 21));
            memoryData <= "11111111000000000000000000000000";
            ramcount <= ramcount + 1;
        elsif ramcount = 1 then
            nadsc <= '0';
                notWE <= '0';
            ramcount <= ramcount + 1;
        elsif ramcount = 2 then
                notWE <= '1';
                nadsc <= '1';
            ramcount <= ramcount + 1;
        elsif ramcount = 3 then
                memoryAddr <= std_logic_vector(to_unsigned(1, 21));
                memoryData <= "00000000111111110000000000000000";
            ramcount <= ramcount + 1;
          elsif ramcount = 4 then                
                nadsc <= '0';
                notWE <= '0';
                ramcount <= ramcount + 1;
          elsif ramcount = 5 then
                notWE <= '1';
                nadsc <= '1';
                data <= (others => 'Z');
                ramcount <= ramcount + 1;
          else
            ramcount <= 0;
            ramst <= read;
        end if;
    when read =>
            if ramcount = 0 then
                     notOE <= '0';
                     memoryAddr <= std_logic_vector(to_unsigned(0, 21));
                ramcount <= ramcount + 1;
            elsif ramcount = 1 then
                nadsc <= '0';
                if data = "11111111000000000000000000000000" then
                    led0 <= '0';
                else
                    led0 <= '1';
                end if;
                ramcount <= ramcount + 1;
            elsif ramcount = 2 then
                if data = "11111111000000000000000000000000" then
                    led1 <= '0';
                else
                    led1 <= '1';
                end if;
                ramcount <= ramcount + 1;
            elsif ramcount = 3 then
                if data = "11111111000000000000000000000000" then
                    led0 <= '0';
                else
                    led0 <= '1';
                end if;
                ramcount <= ramcount + 1;
                elsif ramcount = 4 then
                if data = "11111111000000000000000000000000" then
                    led1 <= '0';
                else
                    led1 <= '1';
                end if;
                ramcount <= ramcount + 1;
                elsif ramcount = 5 then
                     memoryAddr <= std_logic_vector(to_unsigned(1, 21));
                     if data = "00000000111111110000000000000000" then
                    led2 <= '0';
                else
                    led2 <= '1';
                end if;
                     ramcount <= ramcount + 1;
                elsif ramcount = 6 then
                     if data = "00000000111111110000000000000000" then
                    led3 <= '0';
                else
                    led3 <= '1';
                end if;
                     ramcount <= ramcount + 1;
                elsif ramcount = 7 then
                     if data = "00000000111111110000000000000000" then
                    led2 <= '0';
                else
                    led2 <= '1';
                end if;
                     ramcount <= ramcount + 1;
                elsif ramcount = 8 then
                     if data = "00000000111111110000000000000000" then
                    led3 <= '0';
                else
                    led3 <= '1';
                     end if;
                     ramcount <= ramcount + 1;
                elsif ramcount = 9 then
                     nadsc <= '1';
                     notOE <= '1';
            else
                null;
            end if;
    end case;
  end if;
  end process readram_process;
  
 nWE <= '0' when notWE = '0' else '1';
 nOE <= '0' when notOE = '0' else '1';
 nCS <= '0' when notWE = '0' xor notOE = '0' else '1';
 data <= memoryData when notWE = '0' else (others => 'Z');
 nbe0 <= '0' when notWE = '0' else '1';
 nbe1 <= '0' when notWE = '0' else '1';
 nbe2 <= '0' when notWE = '0' else '1';
 nbe3 <= '0' when notWE = '0' else '1';
 addr <= memoryAddr;
end architecture behave;