Forum Discussion
DShat4
New Contributor
New ContributorWriting to SDRAM from FPGA (DE0-Nano-SoC board)
Hi, I have designed a hardware component in VHDL that generates 32-bit data at a rate of 1 MHz. The generated data has to be stored in the SDRAM so that I can read it from the HPS. The problem is th...
- Hello, It depends on the data size. I recommend to use DMA controller and send the data through address span extender to HPS SDRAM, so that HPS can read it. The other approach would be, connecting the H2F bridge to SDRAM controller of FPGA, and read through it. Please let me know if you need further assistance, I have done some data transfer between FPGA and HPS on DE10 nano, which is almost similar to DE0 Nano SoC. Thanks
FawazJ_Altera
Frequent Contributor
Frequent ContributorHello sir,
The DMA will help to offload the data transfer task from Nios II (or any FSM). Its up to you if you want to use it or not.
Choosing SDRAM or OCRAM depends on the data size that you want to hold on FPGA before sending it to HPS.
OCRAM can be helpful since the latency is much lower than the SDRAM. from HPS side, you can access both as long as the Qsys connections are correct.
Thanks
