Forum Discussion
DShat4
New Contributor
New ContributorWriting to SDRAM from FPGA (DE0-Nano-SoC board)
Hi, I have designed a hardware component in VHDL that generates 32-bit data at a rate of 1 MHz. The generated data has to be stored in the SDRAM so that I can read it from the HPS. The problem is th...
- Hello, It depends on the data size. I recommend to use DMA controller and send the data through address span extender to HPS SDRAM, so that HPS can read it. The other approach would be, connecting the H2F bridge to SDRAM controller of FPGA, and read through it. Please let me know if you need further assistance, I have done some data transfer between FPGA and HPS on DE10 nano, which is almost similar to DE0 Nano SoC. Thanks
FawazJ_Altera
Frequent Contributor
Frequent ContributorHello,
It depends on the data size.
I recommend to use DMA controller and send the data through address span extender to HPS SDRAM, so that HPS can read it.
The other approach would be, connecting the H2F bridge to SDRAM controller of FPGA, and read through it.
Please let me know if you need further assistance, I have done some data transfer between FPGA and HPS on DE10 nano, which is almost similar to DE0 Nano SoC.
Thanks
DShat4New Contributor
New ContributorHello FJumaah,
I thought the FPGA could write directly into the SDRAM Controller as a master. Is there any reason why I should use the DMA? Also, I am beginning to doubt using the SDRAM is the best option for my project. I provide more details below.
DETAILS
I have designed an IP core that receives 4 consecutive bytes and concatenates them into a 32-bit word (basically a demux). I need to send the word somewhere so that the processor (running Linux) can pack the data and send it through Ethernet in UDP frames.
Yesterday, I read in other forum that one way to implement something similar is to use an On-Chip RAM with two slave ports (FPGA writes to RAM while HPS reads). Do you think that could work?
