write/read sdram

Sorry for delayed response.

Here is the interface between sdram and my processor:

master_address_dmem:OUT std_logic_vector(31 downto 0);

this is the address to the sdram

0 - 0x0000FFFF space is used for data

0x0001FFFF - onward is reserved for debug symbol i,e; for dumping register contents. The following process reads the register contents when reg_debug (dip switch) is asserted.

The reg_count is index to register file and reg_count is also contacted to data memory address as a least signifcant nibble.

process(reg_debug, clock)

begin

if clock'event and clock = '1' then

if reg_debug = '1' then

if lock = '0' then

reg_count <= reg_count + 1;

end if;

end if;

end if;

end process;

lock <= master_waitrequest_pmem or master_waitrequest_dmem;

master_read_dmem:OUT std_logic;

This the data memory read signal is asserted when loading from the memory.

master_write_dmem:OUT std_logic;

asserted when writing to memory (when storing or debugging )

master_write_dmem <= data_mem_wr_en or reg_debug or pc_debug;

pc-debug is also connected to a dip switch

master_readdata_dmem: IN std_logic_vector(15 downto 0);

data returned from data memory.

master_writeddata_dmem: OUT std_logic_vector(15 downto 0);

data to be written to data memory

master_writeddata_dmem <= op1_dc when reg_debug = '1' else -- writing register file contents

pc(15 downto 0) when pc_debug = '1' else -- wrting pc halfword

data_to_data_mem; -- normal writing to data memory.

master_waitrequest_dmem:IN std_logic;

this wait signal locks the processor and freezes all synchornous processes.

I hope that this explanation will help in understanding my problem. If you need any particular portion of VHDL portion, kindly indicate.

Thanks