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MapleDoi's avatar
MapleDoi
Icon for New Contributor rankNew Contributor
5 years ago

Will FPGA stop working after a huge number of clock pulse. (DE1-SoC)

Hi, I am not sure how to describe the problem to be written in the title. So I have a 150mb dataset in .txt, it looks like: 0.123 0.254 0.956 ... got like 3 million rows. I am using the FIFO in...
EBERLAZARE_I_Intel's avatar
EBERLAZARE_I_Intel
Icon for Regular Contributor rankRegular Contributor
5 years ago

Hi,

Looking at this issue, it might be caused by the timing issue of your design.

Is the design your own or from a tutorial/ websites that you selected?

Which Quartus version are you currently working on? Could you share your timing reports in Quartus here?