Why would assigning a signal as a Global Clock Signal send board into reset?

Usually, we use those signal in the Global as clock or reset. Can you try to move back your signal to local back? if you found that you have too many fan out on your signal, you can just limit it so that quartus will automatically duplicate those register accordingly.

What Quartus version and device that you were using? We have make some improvement on Qpro version for duplicate register in assignment editor.

Moving the signal back to local fixes the issue.

How big is the fanout supported by the global clock buffers?

I'm using Quartus Standard Edition 19.1 with the DE1-SoC board.

How big is the fanout supported by the global clock buffers?

It would be unlimited

The problem is that, if you put your signal to global clock buffers, they might not have any more relationship between your data and clock signal. Since both your clock and data signal are in global clock buffers.

How much fan out that you are looking into? Can you send us the screenshot of the report file showing that?

Also, usually, high fan out happened on the register, can you add additional register before the combi to have the high fan out?

Is there another recommendation for routing a signal to many nodes in a way that efficiently utilizes the available routing resources?

What I would suggest is used design partition, this way, you can preserve the routing and it will not cause other logic to interfere with your high fan out combi.

Good to hear that design partition was helpful. Let us know if this solution is sufficient?

Any update?

The design partition solution is sufficient for my purposes. Thank you