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Jiayi_H_Intel's avatar
Jiayi_H_Intel
Icon for Occasional Contributor rankOccasional Contributor
6 years ago

Why LVDS output clock must be divided by division factor?

Hi experts, I am using LVDS transmitter with internal PLL, on 10M50 board. Just find that tx_outclock must be divided by a division factor, which has some fixed value: 10, 2, 4, 20. Why can't we ju...
YuanLi_S_Intel's avatar
YuanLi_S_Intel
Icon for Regular Contributor rankRegular Contributor
5 years ago

Hi Jiayi,

The division is actually the factor convertion from LVDS fast clock to tx_outclock. Fast clock is a high frequency that is converted from user supply clock and it is meant for the mechanism of LVDS.

You will need to refer to the serialization factor that you choose for the setting of the division.

For more information, please refer to our user guide for that:

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_altera_lvds.pdf (Page 18)

Thank You

Jiayi_H_Intel's avatar
Jiayi_H_Intel
Icon for Occasional Contributor rankOccasional Contributor
5 years ago

That means if I set data rate to 200Mbps, and serialization factor is 10. I can choose 10, 2, 4 or 20 for division factor in drop list. So the fastest output clock is 100M( division factor is 2), right?