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FVanE1's avatar
FVanE1
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6 years ago

Why is the GTX clock output of the HPS running at 250 MHz?

We have an Arria 10 FPGA with ARM processor. In Platform Designer one of the EMACs is routed to the FPGA logic. We do not route the GMII Tx data and GTX clock directly from FPGA logic to a PHY, but we want to merge this data stream with other data and send it to a 10G optical link.

If we run the FPGA logic at the GTX clock output of the HPS system, we see each data byte of the GMII interface is sent twice. When measuring the GTX clock we see a frequency of 250 MHz. While we expect 125 MHz for a fixed 1 Gbps interface.

Can someone explain me why the GTX clock output is running at a frequency which is twice the expected frequency?

Best regards,

Frank

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  • EBERLAZARE_I_Intel's avatar
    EBERLAZARE_I_Intel
    Icon for Regular Contributor rankRegular Contributor
    5 years ago

    Hi,

    I apologize for the long response time due the current situation, thus I have overlooked this case. The only close fix that I could find regarding your issue, there seems to be an issue in the previous version of Quartus when changing the clock of the EMAC, and there are changes/patch made in the latest 18.1 on-ward, thus we recommend that you try to use the latest version of Quartus preferably 19.1, to see if this fixes your issue.

    If further support is required, please post a response in the next few days to allow me to continue to support you. This thread will be transitioned to community support. The community users will be able to help you with your follow-up questions.

  • FVanE1's avatar
    FVanE1
    Icon for New Contributor rankNew Contributor
    5 years ago

    Hi,

    Since we have a workaround, this issue can be closed.

    Thank you for your help.

    Best regards,

    Frank van Eijkelenburg