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FVanE1's avatar
FVanE1
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6 years ago

Why is the GTX clock output of the HPS running at 250 MHz?

We have an Arria 10 FPGA with ARM processor. In Platform Designer one of the EMACs is routed to the FPGA logic. We do not route the GMII Tx data and GTX clock directly from FPGA logic to a PHY, but w...
EBERLAZARE_I_Intel's avatar
EBERLAZARE_I_Intel
Icon for Regular Contributor rankRegular Contributor
5 years ago

Hi,

After the compilation for Arria 10 SoC in quartus, there is a folder called hps_isw_handoff, you can open the hps.xml using text editor and check the hps clk user0 and user 1 value, which is 400000000 in the default GHRD.

FVanE1's avatar
FVanE1
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5 years ago

Hi,

When I change the EMAC1 emac1_gtx_clk clock frequency into 125 MHz (tab "HPS Clocks and reset, Input Clocks") this frequency is not found in the hps.xml. This hps.xml file mentions the emac1_clk_hz frequency of 250 MHz which is (I assume) the value of the EMAC 1 clock frequency (tab "HPS Clocks and reset, Internal Clocks and Output Clocks").

Best regards,

Frank